1 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus december 2001 2001 integrated device technology, inc. dsc 5855/4 c industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? 3.3v operation ? 4 pairs of programmable skew outputs ? low skew: 150ps same pair, 350ps all outputs ? selectable positive or negative edge synchronization: excellent for dsp applications ? synchronous output enable ? input frequency: 25mhz to 225mhz ? output frequency: 25mhz to 225mhz ? 2x, 4x, 1/2, and 1/4 outputs (of vco frequency) ? 3-level inputs for skew control ? pll bypass for dc testing ? external feedback, internal loop filter ? 12ma balanced drive outputs ? low jitter: <150ps peak-to-peak ? available in 144-pin bga package functional block diagram idt5v996 3.3v programmable skew pll clock driver turboclock tm ii plus pll skew select 1f2:0 skew select 4f2:0 skew select 3f2:0 skew select 2f2:0 lock fb ref test 1q0 1q1 2q0 2q1 3q0 3q1 4q0 4q1 3 3 3 se enable logic 3 3 3 3 3 3 3 3 3 g description: the idt5v996 is a high fanout pll based clock driver intended for high performance computing and data-communication applications. the idt5v996 has eight programmable skew outputs organized in four banks of two. skew is controlled by 3-level input signals that may be hard wired to appropriate high-mid-low levels. the idt5v996 provides up to 18 programmable levels of output skew, prescaling, and other features. other features of idt5v996 are synchronous output enable (g), test, and lock detect indicator (lock). when g is held low, all the outputs are synchronously enabled, however, if g is held high, all outputs except 3q0 and 3q1 are in the state designated by se (high or low). when test is held low, the chip operates in normal condition. when held high, the pll is shut off and the chip functions as a buffer. the lock detect indicator asserts high when the phase lock loop has acquired lock. during acquisition, the indicator is in the low state. once the pll has reached the steady-state condition within a specified frequency range, lock is asserted high. the pll is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. the idt5v996 has lvttl outputs with 12ma balanced drive outputs. the idt5v996 is characterized for operation from ?40c to +85c.
2 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus pin configuration a b c d e f g h j k l m a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 11 12 1 2 g ref fb se v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 3 4 5 6 7 89 10 11 12 v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq test 2q1 2q0 1q1 1q0 lock 2f2 2f0 1f1 4f1 3f0 3f2 2f1 1f2 1f0 4f0 4f2 3f1 3q1 3q0 4q1 4q0 v ddq v ddq v ddq v ddq v dd v dd v dd v dd v dd v dd v dd v dd gnd gnd v dd v dd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v dd v dd gnd gnd gnd gnd gnd gnd v dd v dd gnd gnd gnd gnd gnd gnd v dd v dd gnd gnd gnd gnd gnd gnd v dd v dd gnd gnd gnd gnd gnd gnd v dd v dd gnd gnd gnd gnd gnd gnd v ddq v ddq v ddq v ddq v dd v dd v dd v dd v dd v dd v dd v dd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq bga top view
3 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. output skew with respect to the ref input is adjustable to compensate for pcb trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked compo- nents. skew is selectable as a multiple of a time unit (t u ) which ranges from 278ps to 625ps (see programmable skew range and resolution table). there are 16 skew configurations available for each output pair. these configurations are chosen by the nf 2:0 control pins. in order to minimize the number of control pins, 3-level inputs (high-mid-low) are used, they are intended for but not restricted to hard-wiring. undriven 3-level inputs default to the mid level. where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. the control summary table shows how to select specific skew taps by using the nf 2:0 control pins. programmable skew absolute maximum ratings (1) symbol description max unit v ddq , v dd supply voltage range ?0.5 to +4.6 v v i (2) input voltage range ?0.5 to 4.6 v v o (2) voltage range applied to any ?0.5 to v output in the high or low state v ddq + 0.5 i ik (v i < 0) input clamp current ?50 ma i o (v o = 0 to v ddq ) continuous output current 50 ma v ddq or gnd continuous current 100 ma t stg storage temperature range ?65 to +150 c notes: 1. unused inputs must be held high or low to prevent them from floating. 2. capacitance applies to all inputs except nf 2:0 . this value is characterized but not production tested. capacitance (1,2) (t a = +25c, f = 1mhz, v in = 0v) parameter description min typ. max. unit c in input capacitance ? 8 ? pf v i = v ddq or gnd pin description pin name type description ref i n reference clock input se i n selectable positive or negative edge control. when low / high, the outputs are synchronized with the negative/positive edg e of the reference clock. when outputs are synchronously stopped with the g pin, se determines the level at which outputs stop. when s e is low/high, outputs synchronously stop high/low. fb i n feedback input g i n output gate for ?true? nq [1:0] outputs. when g is low, the ?true? nq [1:0] outputs are enabled. when g is high, the ?true? nq [1:0] outputs are in the state designated by se (high or low) (except 3q 0 and 3q 1 ) - 3q 0 and 3q 1 may be used as the feedback signal to maintain phase lock. test i n test = low means normal operation. test = high means that the pll is powered down and ref is routed to all the outputs. the skews selected with the nf [2:0] pins are still in effect. (the test pin is a ttl input.) nf[ 2:0 ] i n 3-level inputs for selecting 1 of 18 skew taps or frequency functions nq[ 1:0 ] out clock output pairs v ddq pwr power supply for output buffers v dd pwr power supply for phase locked loop and other internal circuitry gnd pwr ground lock out lock detect. asserted (high) when the pll is locked. the ref input must be oscillating.
4 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus external feedback by providing external feedback, the idt5v996 gives users flexibility with regard to skew adjustment. the fb signal is compared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust upwards or downwards accordingly. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accu- rate responses to input frequency changes. control summary table for feedback signals (1) nf 2 nf 1 nf 0 output skew l l l disable (2) l h l -7t u l h m -6t u l h h -5t u m l l -4t u m l m -3t u m l h -2t u m m l -1t u m m m zero skew m m h +1t u m h l +2t u m h m +3t u m h h +4t u h l l +5t u h l m +6t u h l h +7t u h m l inverted h m m divide by 2 h m h divide by 4 comments timing unit calculation (t u ) 1/(16 x f nom ) vco frequency range (f nom ) (1) 100 to 225 mhz skew adjustment range (2) max adjustment: 4.375ns ns 157.5 phase degrees 43.75% % of cycle time example 1, f nom = 100mhz t u = 0.625ns ? example 2, f nom = 167mhz t u = 0.374ns ? example 3, f nom = 225mhz t u = 0.278ns ? pll programmable skew range and resolution table notes: 1. the vco frequency always appears at nq 1:0 outputs when they are operated in their undivided modes. the frequency appearing at the ref and fb inputs will be f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs will be f nom /2 or f nom /4 when the part is configured for frequency multiplication by using a divided output as the fb input. using the nf[ 2:0 ] inputs allows a different method for frequency multiplication (see control summary table for feedback signals). 2. skew adjustment range assumes that a zero skew output is used for feedback. if a skewed q output is used for feedback, then a djustment range will be greater. for example if a 4t u skewed output is used for feedback, all other outputs will be skewed ?4t u in addition to whatever skew value is programmed for those outputs. ?max adjustment? range applies to all output pairs where 7t u skew adjustment is possible and at the lowest f nom value. notes: 1. all unused/unnoted combinations are reserved. 2. when g is low, all output pairs are individually disabled to the level designated by se. when se is low/high, output pairs d isable high/low.
5 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus recommended operating range symbol description min. typ. max. unit v dd / v ddq power supply voltage 3 3.3 3.6 v t a ambient operating temperature -40 +25 +85 c power supply characteristics symbol parameter test conditions (1) typ. (2) max. unit i ddq quiescent power supply current v ddq = max., ref = fb = se = g = low, ? 30 ma test = high, all nf 2:0 = hhm (3) , all outputs floating i ddd dynamic power supply current per output v ddq = max., c l = 0pf 410 650 a/mhz v ddq = 3.3v, f vco = 100mhz, c l = 20pf 124 ? i tot total power supply current v ddq = 3.3v, f vco = 167mhz, c l = 20pf 197 ? ma v ddq = 3.3v, f vco = 225mhz, c l = 20pf 253 ? notes: 1. measurements are for divide-by-1 outputs. 2. for nominal voltage and temperature. 3. this configuration is only specific for i ddq measurements. dc electrical characteristics over operating range symbol parameter conditions min. max. unit v ih input high voltage guaranteed logic high (ref, fb inputs only) 2 ? v v il input low voltage guaranteed logic low (ref, fb inputs only) ? 0.8 v v ihh input high voltage level (1) 3-level inputs only v dd ? 0.6 ? v v imm input mid voltage level (1) 3-level inputs only v dd /2 ? 0.3 v dd /2+0.3 v v ill input low voltage level (1) 3-level inputs only ? 0.6 v i in input leakage current v in = v cc or gnd -5 +5 a (ref, fb inputs only) v cc = max. v in = v dd high level ? +200 i 3 3-level input dc current (nf 2:0 )v in = v dd /2 mid level -50 +50 a v in = gnd low level -200 ? v oh output high voltage level v dd = min., i oh = ? 12ma 2.4 ? v v ol output low voltage level v dd = min., i ol = 12ma ? 0.4 v note: 1. these inputs are normally wired to v ddq , gnd, or unconnected. internal termination resistors bias unconnected inputs to v ddq /2. if these inputs are switched, the function and timing of the outputs may be glitched, and the pll may require an additional t lock time before all datasheet limits are achieved.
6 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus notes: 1. measured at v th = v ddq /2, output load c l = 20pf. 2. skew is the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with the specified load. 3. t skewpr is the skew between a pair of outputs (xq 0 and xq 1 ) when all eight outputs are selected for 0t u . 4. there are 3 classes of outputs: nominal (multiple of t u delay), inverted, and divided (divide-by-2 or divide-by-4 mode). 5. t dev is the output-to-output skew between any two devices operating under the same conditions (v dd and v ddq , ambient temperature, air flow, etc.) 6. t lock is the time that is required before synchronization is achieved. this specification is valid only after v dd and v ddq are stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. 7. t odcv is measured with nf [2:0] = mmm. switching characteristics over operating range (1) symbol parameter min. typ. max. unit f nom vco frequency range see pll programmable skew range and resolution table f ref ref clock input frequency 25 ? 225 mhz t ref ref clock duty cycle 10 ? 90 % t u programmable skew time unit see control summary table t skewpr matched-pair skew (xq 0 , xq 1 ) (1,2,3) ? ? 150 t sk(0) output skew (rise-rise, fall-fall, same frequency and phase) (1,2) ? ? 350 t sk( ) multiple frequency skew (1,2) ? ? 550 t sk(inv) inverting skew between nominal and inverted (1,2,4) ? ? 500 t skew1 output skew (rise-fall, inverted-divided) (1,2) ? ? 500 ps t skew4 output skew (rise-fall, divided-divided) (1,2,4) ? ? 500 t dev device-to-device skew (2,5) ? ? 250 t ref input to fb static phase offset (v th = v ddq /2) -250 ? +250 t odcv output duty cycle variation from 50% (1,7) -0.75 ? +0.75 ns t r output rise time (0.8v to 2v) (1) ? ? 2.2 ns t f output fall time (2v to 0.8v) (1) ? ? 2.2 ns t lock pll lock time (6) ? ? 0.5 ms t j cycle-to-cycle output jitter, peak-to-peak (1) ? ? 150 ps
7 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus c l = 20pf 150 ? 150 ? nqn fb idt5v996 f bout pcb trace 3q 0 ref c f 2 0.8 v th t r t f 3v v th =v ddq /2 0v 20pf 150 ? 150 ? output ac test loads and waveforms output waveform input waveform ac load notes: 1. v th = v ddq /2. 2. c f = c l - c fbin - c pcbtrace ; c fbin ? 6pf 3. calculations were done by adjusting the input slew rate to match with the output slew rate. static phase offset and skew calculations (2,3)
8 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus ac timing diagram t j ref fb q other q inverted q ref divided by 2 ref divided by 4 t ref t sk(inv) t skew1,4 t sk( ) t sk(inv) t skewpr t sk(o) t rpwh t rpwl t skewpr t sk(o) t ( ) t sk( ) t skew1,4 t sk( ) t odcv t odcv notes: se: the ac timing diagram applies to se=v dd . for se=gnd, the negative edge of fb aligns with the negative edge of ref, divided outputs change on the negative edge of ref, and the positive edges of the divide-by-2 and the divide-by-4 signals align. skew: the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 20pf and terminated with 75 ? to v ddq /2. t skewpr : the skew between a pair of outputs (xq 0 and xq 1 ) when all eight outputs are selected for 0t u . t sk(0) : the skew between outputs when they are selected for 0t u . t dev : the output-to-output skew between any two devices operating under the same conditions (v ddq , v dd , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew1 and t skew4 specifications. t sk( ): the skew between outputs of different frequencies. t sk(inv): the skew between inverting and non-inverting outputs. t r and t f are measured between 0.8v and 2v. t lock : the time that is required before synchronization is achieved. this specification is valid only after v dd /v ddq is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
9 industrial temperature range idt5v996 3.3v programmable skew pll clock driver turboclock ii plus ordering information idt xxxxx package device type 5v996 3.3v programmable skew pll clock driver turboclock ii plus plastic ball grid array bb xx process x -40c to +85c (industrial) i corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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